(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a buried stack capacitor structure.
(2) Description of Prior Art
Buried stack capacitor structures, used as components for dynamic random access memory (DRAM), as well as for static random access memory (SRAM), devices can in part be formed via a chemical mechanical polishing (CMP) procedure applied to a polysilicon layer, defining the polysilicon storage node for these devices. However the topography presented prior to the formation of the buried stack capacitor, polysilicon storage node structure, can sometimes result in unwanted polysilicon stringers, or residual polysilicon, located between individual storage node structures, or between a storage node structure and an adjacent component. The combination of severe topography, excellent contouring properties of chemically vapor deposited polysilicon layers, and anisotropic dry etch, or CMP procedures, increase the risk of polysilicon stringers or residuals on the sides of isolation features. In addition the CMP procedure, used to define a bottom polysilicon node, or polysilicon storage node structure, terminating on a polysilicon surface, can result in unwanted roughness, or damage of, the top surface of the polysilicon storage node structure, sometimes resulting in leakage exhibited by a subsequently formed, overlying dielectric layer.
This invention will teach a process sequence used to form the bottom electrode of buried stack capacitor structures, in which polysilicon stringers and residuals, are eliminated. The process sequence employs the use of a silicon oxide layer on the polysilicon layer used for the bottom electrode structure, photoresist planarization, etch back, and selective wet etch procedures, with the combination of these procedures resulting in buried stacked capacitor structures, absent of the yield degrading polysilicon stringers and polysilicon residuals. Prior art, such as Huang et al, in U.S. Pat. No. 5,723,374, describe a process for preventing polysilicon stringers in stacked capacitor DRAM devices, however that prior art does not employ the unique combination of process steps described in this present invention, used to improve the yield of devices featuring buried stacked capacitor structures, via the elimination of polysilicon stringers and residuals.
It is an object of this invention to fabricate buried stack capacitor structures for DRAM, and SRAM devices, in recesses formed in shallow trench isolation (STI) regions.
It is another object of this invention to deposit an insulator layer on the blanket polysilicon layer to be used for the bottom electrode, or storage node structure, of the buried stack capacitor structure.
It is still another object of this invention to employ photoresist planarization and etch back procedures to form protective photoresist plugs on the storage node materials located in the STI recessed regions, during the dry etch procedures used to remove these same materials located in other regions of the device.
In accordance with the present invention a process sequence used to form buried stack capacitor structures in recesses in an STI region, featuring photoresist planarization, and selective etching procedures used to form the buried stack capacitor polysilicon storage node component, used to eliminate polysilicon stringers, and used to minimize polysilicon damage during the storage node definition process, is described. After formation of an STI region in a top portion of a semiconductor substrate, a silicon nitride layer is deposited and patterned with openings in the silicon nitride layer exposing portions of the STI region. Recesses in the STI region are formed using the openings in the silicon nitride as a mask to allow for subsequent accommodation of the buried stack capacitor structure, with an unetched portion of STI, or OD, (wherein OD is oxide defined, active device region of the semiconductor substrate), overlaid with an unetched portion of silicon nitride, located between the recesses in the STI region. A polysilicon layer is deposited, followed by the deposition of a silicon oxide layer. A planarizing photoresist layer is formed, followed by etch back of the photoresist layer exposing the top surface of the silicon oxide layer in regions in which silicon oxide and the underlying polysilicon layer are not located in the recessed regions of, or in the bins of, the STI region, while unremoved regions of the photoresist layer, or photoresist plugs, remain overlying the silicon oxide and polysilicon layers located in the STI recesses. After selective removal of the exposed regions of silicon oxide, now exposed portions of polysilicon are removed, resulting in the definition of individual, isolated, polysilicon bottom electrode, or storage node structures, each located in an STI recess. The unwanted portions of polysilicon are either removed via a dry etching procedure, with the photoresist plugs in the recessed STI regions still remaining, or via wet etch procedure, performed after removal of the photoresist plug. Removal of silicon oxide located on the polysilicon storage node structure is followed by selective removal of silicon nitride, exposing an active device region. Formation of a capacitor dielectric layer, on the polysilicon storage node structure, followed by formation of an overlying top electrode structure, complete the formation of the buried stack capacitor structure.